1. Field of the Invention
This invention relates to packaging of LSI chips and more particularly to the problem of providing capacitors with relatively high values located near the chips with ultra-low inductance connections between the chips and the capacitors.
2. Description of the Prior Art
Narken et al "Low Capacitive Via Path Through High Dielectric Constant Material" IBM Technical Disclosure Bulletin 22, No. 12, 5330-1 (May 1980) describes a decoupling capacitor located in a multilayer structure directly below a chip with vias extending through the dielectric material of the capacitors. The arrangement is intended to minimize the inductance of the structure.
Lussow "Internal Capacitors and Resistors for Multilayer Ceramic Modules" IBM Technical Disclosure Bulletin 20, No. 9, 3436-7 (February 1978) describes a multilayer ceramic module with capacitors incorporated within the green sheet structure.
No prior art has been found which suggests in any way the provision of the aligned connector wires extending in opposite directions in order to cancel out magnetic flux induced by currents in the leads to the capacitor. Nor does the prior art suggest the formation of a capacitor with multiple segments located within the body of the carrier connected in such a way that they are adapted for easy mechanical or laser deletion to alter the capacitance of the capacitor or to remove defects subsequent to fabrication.